1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to improvement in a memory device in which each memory cell comprises one or more high-resistance elements.
2. Description of the Background Art
Referring to FIG. 1, a circuit diagram of one example of a memory cell comprising one or more high-resistance elements is shown. The memory cell is one of the known SRAMs (Static Random Access Memories) and comprises four transistors T and two high-resistance elements 3a. The memory cell is connected to a supply potential Vcc and a ground potential GND, and information is written into the memory cell or read therefrom through a bit line pair BL, BL in response to a signal on a word line WL.
FIG. 2 shows a top view of a part of a memory device comprising a plurality of memory cells of FIG. 1. These memory cells are arranged in a matrix on a semiconductor substrate. Four transistors in each memory cell are formed in one of rectangular transistor regions 1 on the semiconductor substrate. Two high-resistance elements 3a in a memory cell are formed in a high-resistance element region 2a of the same rectangular shape as transistor region 1 in a resistor layer overlying transistor region 1. Illustration of interconnecting lines is omitted in FIG. 2 for clarity of the drawing.
In a conventional high-resistance-load-type SRAM device having a memory capacity of less than 1 megabit, a high-resistance element region 2a has the same area and the same shape as those of a transistor region 1. The fact that high-resistance element region 2a has the same shape as that of transistor region 1 offers great advantage to designing of a SRAM device and particularly to designing of a pattern layout.
In a highly integrated high resistance load-type SRAM device having a memory capacity of more than 1 megabit, however, it is necessary to make transistor region 1 further smaller and to make high-resistance element region 2a also smaller in accordance with it. However, it is difficult to form a small high-resistance element with high precision in comparison with the case of forming a small transistor.
On the other hand, it is desired to form a high-resistance element 3a with high precision from the standpoint of the data holding characteristics, power consumption during waiting or the like of a SRAM device. For example, in a SRAM device having a memory capacity of more than 1 megabit, while one high-resistance element 3a is designed to have one target resistance value within a range of 3 to 30T.OMEGA., the resistance value of an actually formed high-resistance element 3a must be controlled so as not to include an error exceeding approximately .+-.20%.
A high-resistance element 3a is normally formed of polycrystalline silicon film. The resistance value of high-resistance element 3a is controlled mainly by controlling its thickness, length, width and so on. However, the following problems (1)-(3) arose in the case of forming a high-resistance element 3a having a high resistance value within the range of 3-30T.OMEGA. with high precision.
(1) If the thickness of polycrystalline silicon is made smaller in order to increase the resistance value, variations in the resistance value increase suddenly.
(2) If the length of high-resistance element 3a is increased in order to increase the resistance value, high-resistance element region 2a becomes larger, and the area occupied by one memory cell becomes larger.
(3) Reduction in the width of high-resistance element 3a for increasing the resistance value is limited by precision of pattern transcription.